UVM Test
Table of Contents
The user-defined test is derived from uvm_test, uvm_test is inherited from uvm_component.
- The test defines the test scenario for the testbench
- test class contains the environment, configuration properties, class overrides etc
- A sequence/sequences are created and started in the test
The UVM testbench is activated when the run_test() method is called, the global run_test() task should be specified inside an initial block.
initial begin run_test(); end
There can be many user-defined test cases.Among multiple test cases, a particular test case can be selected and execute on two methods,
1. by specifying the test name as an argument to run_test();
example: run_test("mem_model_test");
2. by providing the UVM_TESTNAME command line argument
example: <SIMULATION_COMMANDS> +UVM_TESTNAME=mem_model_test
Writing Test
1. The test is written by extending the UVM_TEST,
class mem_model_test extends uvm_test;
`uvm_component_utils(mem_model_test)
function new(string name = "mem_model_test",uvm_component parent=null);
super.new(name,parent);
endfunction : new
endclass : mem_model_test
2. Declare env and sequence,
mem_model_env env; mem_sequence seq;
3. Create env and sequence,
env = mem_model_env::type_id::create("env",this);
seq = mem_sequence::type_id::create("seq");
4. Start the sequence,
seq.start(env.mem_agnt.sequencer);
Complete Test code,
class mem_model_test extends uvm_test;
`uvm_component_utils(mem_model_test)
mem_model_env env;
mem_sequence seq;
function new(string name = "mem_model_test",uvm_component parent=null);
super.new(name,parent);
endfunction : new
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
env = mem_model_env::type_id::create("env", this);
seq = mem_sequence::type_id::create("seq");
endfunction : build_phase
task run_phase(uvm_phase phase);
seq.start(env.mem_agnt.sequencer);
endtask : run_phase
endclass : mem_model_test