Category: Interview Questions

SystemC Interview Questions

Below are the most frequently asked SystemC interview questions,

  1. What is SystemC SC_HAS_Process?
  2. What is the difference between SystemC sc_int and sc_bigint ?
  3. What is the difference between SystemC SC_METHOD and SC_THREAD?
  4. what are different types of sensitivity in SystemC?
  5. SC_METHOD is preferable over SC_THREAD. Why?
  6. what is context switching in SC_THREAD?
  7. Explain the SystemC simulation kernel?
  8. what is virtual prototyping?
  9. What is the end of elaboration and before the end of elaboration?
  10. what is SC_ZERO_TIME?
  11. What is the difference between sc_port and sc_export?
  12. What are the features of TLM 2.0
  13. What is the difference between TLM 1.0 to TLM 2,0?
  14. What are the different transport interfaces in TLM 2.0?
  15. Difference between method and thread?
  16. Which one you choose for implementation?
  17. what is sc_zero_time in System C and what is the use?
  18. What is the use of dont_initilazie?
  19. Explain SystemC next_trigger and wait difference?
  20. Why is utility sockets are under the non-interoperable layer?
  21. Explain the Debug and Direct memory interface?
  22. What is temporal decoupling?
  23. Explain mutex and semaphore?

SOC Verification Interview Questions

  1. What is the difference between SOC and IP Verification?
  2. Write a block diagram of SOC architecture?
  3. What is the target of verification in SOC verification?
  4. Is coverage is considered in SOC Verification?
  5. What are the major components in SOC architecture?
  6. What are the challenges of SOC verification?

UVM Interview Questions

UVM Interview Questions


Below are the most frequently asked UVM Interview Questions,

    1. What is uvm_transaction, uvm_seq_item, uvm_object, uvm_component?
    2. What is the advantage of  `uvm_component_utils() and `uvm_object_utils() ?
    3. What is the difference between `uvm_do and `uvm_ran_send?
    4. diff between uvm_transaction and uvm_seq_item?
    5. What is the difference between uvm _virtual_sequencer and uvm_sequencer?
    6. What are the benefits of using UVM?
    7. What is the super keyword? What is the need of calling super.build() and super.connect()?
    8. Is uvm is independent of systemverilog ?
    9. Can we have a user-defined phase in UVM?
    10. What is p_sequencer?
    11. What is the uvm RAL model? why it is required?
    12. What is the difference between new() and create?
    13. What is an analysis port?
    14. What is TLM FIFO?
    15. How the sequence starts?
    16. What is the difference between UVM RAL model backdoor write/read and front door write/read?
    17. What is an objection?
    18. What is the advantage of `uvm_pre_body and `uvm_post_body?
    19. What is the difference between Active mode and Passive mode?
    20. What is the difference between copy and clone?
    21. What is the UVM factory?
    22. What are the types of sequencer? Explain each?
    23. What are the different phases of uvm_component? Explain each?
    24. How set_config_* works?
    25. What are the advantages of the uvm RAL model?
    26. What is the different between set_config_* and uvm_config_db?
    27. What are the different override types?
    28. What is virtual sequence and virtual sequencer?
    29. Explain the end of the simulation in UVM?
    30. How to declare multiple imports?
    31. What is the symbolic representation of port, export and analysis port?
    32. What is the difference in usage of $finish and global stop request in UVM?
    33. Why we need to register class with the uvm factory?
    34. can we use set_config and get_config in sequence?
    35. What is the uvm_heartbeat ?
    36. how to access DUT signal in uvm_component/uvm_object?

SV Interview Questions

SystemVerilog Interview Questions

Below are the most frequently asked SystemVerilog Interview Questions,

  1. What is the difference between an initial and final block of the systemverilog?
  2. Explain the simulation phases of SystemVerilog verification?
  3. What is the Difference between SystemVerilog packed and unpacked array?
  4. What is “This ” keyword in the systemverilog?
  5. What is alias in SystemVerilog?
  6. randomized in the systemverilog test bench?
  7. in SystemVerilog which array type is preferred for memory declaration and why?
  8. How to avoid race round condition between DUT and test bench in SystemVerilog verification?
  9. What are the advantages of the systemverilog program block?
  10. What is the difference between logic and bit in SystemVerilog?
  11. What is the difference between datatype logic and wire?
  12. What is a virtual interface?
  13. What is an abstract class?
  14. What is the difference between $random and $urandom?
  15. What is the expect statements in assertions?
  16. What is DPI?
  17. What is the difference between == and === ?
  18. What are the system tasks?
  19. What is SystemVerilog assertion binding and advantages of it?
  20. What are parameterized classes?
  21. How to generate array without randomization?
  22. What is the difference between always_comb() and always@(*)?
  23. What is the difference between overriding and overloading?
  24. Explain the difference between deep copy and shallow copy?
  25. What is interface and advantages over the normal way?
  26. What is modport and explain the usage of it?
  27. What is a clocking block?
  28. What is the difference between the clocking block and modport?
  29. System Verilog Interview Questions, Below are the most frequently asked questions.
  30. What are the different types of verification approaches?
  31. What are the basic testbench components?
  32. What are the different layers of layered architecture?
  33. What is the difference between a $rose and @ (posedge)?
  34. What is the use of extern?
  35. What is scope randomization?
  36. What is the difference between blocking and non-blocking assignments?
  37. What are automatic variables?
  38. What is the scope of local and private variables?
  39. How to check if any bit of the expression is X or Z?
  40. What is the Difference between param and typedef?
  41. What is `timescale?
  42. Explain the difference between new( ) and new[ ] ?
  43. What is the difference between task and function in class and Module?
  44. Why always blocks are not allowed in the program block?
  45. Why forever is used instead of always in program block?
  46. What is SVA?
  47. Explain the difference between fork-join, fork-join_none, and fork- join_any?
  48. What is the difference between mailboxes and queues?
  49. What is casting?
  50. What is inheritance and polymorphism?
  51. What is callback?
  52. What is constraint solve-before?
  53. What is coverage and what are different types?
  54. What is the importance of coverage in SystemVerilog verification?
  55. When you will say that verification is completed?
  56. What are illegal bins? Is it good to use it and why?
  57. What is the advantage of seed in randomization?
  58. What is circular dependency?
  59. What is “super “?
  60. What is the input skew and output skew in the clocking block?
  61. What is a static variable?
  62. What is a package?
  63. What is the difference between bit [7:0] and byte?
  64. What is randomization and what can be
  65. What are the constraints? Is all constraints are bidirectional?
  66. What are in line constraints?
  67. What is the difference between rand and randc?
  68. Explain pass by value and pass by ref?
  69. What are the advantages of cross-coverage?
  70. What is the difference between associative and dynamic array?
  71. What is the type of SystemVerilog assertions?
  72. What is the difference between $display,$strobe,$ monitor?
  73. Can we write SystemVerilog assertions in class?
  74. What is an argument pass by value and pass by reference?

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