foreach loop

SystemVerilog foreach specifies iteration over the elements of an array. the loop variable is considered based on elements of an array and the number of loop variables must match the dimensions of an array.

foreach loop syntax

foreach(<variable>[<iterator>]]) begin
  //statement - 1
  ...
  //statement - n
end

Foreach loop iterates through each index starting from index 0.

foreach loop example

below example shows,
foreach loop in the single dimensional array.

module for_loop;
  int a[4];
  initial begin
    $display("-----------------------------------------------------------------"); 
    foreach(a[i]) a[i] = i;
    foreach(a[i]) $display("\tValue of a[%0d]=%0d",i,a[i]);
 
    $display("-----------------------------------------------------------------");
  end   
endmodule

Simulator Output

-----------------------------------------------------------------
Value of a[0]=0
Value of a[1]=1
Value of a[2]=2
Value of a[3]=3
-----------------------------------------------------------------

Click to execute on

foreach multidimensional array

Below example shows how to use the foreach loop in a multidimensional array.

module for_loop;
  int a[3][2];

  initial begin
    $display("-----------------------------------------------------------------");
    foreach(a[i,j]) a[i][j] = i+j;
    foreach(a[i,j]) $display("\tValue of a[%0d][%0d]=%0d",i,j,a[i][j]);  
    $display("-----------------------------------------------------------------");
  end    
endmodule

Simulator Output

-----------------------------------------------------------------
 Value of a[0][0]=0
 Value of a[0][1]=1
 Value of a[1][0]=1
 Value of a[1][1]=2
 Value of a[2][0]=2
 Value of a[2][1]=3
-----------------------------------------------------------------

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do while loop

A do while loop is a control flow statement that allows code to be executed repeatedly based on a given condition.

do while loop syntax

    do begin
        // statement -1       
        ...
        // statement -n 
    end
    while(condition);

In do-while,

• the condition will be checked after the execution of statements inside the loop
• the condition can be any expression.

do-while is similar to while loop but in case of while loop execution of statements happens only if the condition is true. In a do while, statements inside the loop will be executed at least once even if the condition is not satisfied.

do while loop example

module do_while;
  int a;
 
  initial begin
    $display("-----------------------------------------------------------------");

    do
      begin
        $display("\tValue of a=%0d",a);
        a++;
      end
    while(a<5);
  
    $display("-----------------------------------------------------------------");
  end    
endmodule

Simulator output:

-----------------------------------------------------------------
Value of a=0
Value of a=1
Value of a=2
Value of a=3
Value of a=4
-----------------------------------------------------------------

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do while loop example 2

module do_while;
  int a;
 
  initial begin
    $display("-----------------------------------------------------------------");
   
    do
      begin
        $display("\tValue of a=%0d",a);
        a++;
      end
    while(a>5);

    $display("-----------------------------------------------------------------");
  end
endmodule

Simulator Output

-----------------------------------------------------------------
Value of a=0
-----------------------------------------------------------------

Click to execute on

while loop SystemVerilog

A while loop is a control flow statement that allows code to be executed repeatedly based on a given condition.

while loop syntax

    while(condition) begin
        // statement -1       
        ...
        // statement -n 
    end

In a while,

• Execution of statements within the loop happens only if the condition is true

while loop example

module while_loop;
  int a;

  initial begin
    $display("-----------------------------------------------------------------");

    while(a<5)
      begin
        $display("\tValue of a=%0d",a);
        a++;
    end
    $display("-----------------------------------------------------------------");
  end    
endmodule

Simulator Output

-----------------------------------------------------------------
Value of a=0
Value of a=1
Value of a=2
Value of a=3
Value of a=4
-----------------------------------------------------------------

Click to execute on

while loop example 2

module while_loop;
  int a;
  initial begin
    $display("-----------------------------------------------------------------");

    while(a>5)
      begin
        $display("\tValue of a=%0d",a);
        a++;
      end
    $display("-----------------------------------------------------------------");
  end     
endmodule

Simulator Output

-----------------------------------------------------------------
-----------------------------------------------------------------

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SystemVerilog Randomization and SystemVerilog Constraint

This section provides object-based randomization and constraint programming, explanation on random variables, randomization methods and constraint blocks.

• Randomization
• Disable Randomization
• Randomization methods
• Constraints
  • Constraint Block, External Constraint Blocks and Constraint Inheritance
  • Inside Operator
  • Weighted Distribution
  • Implication Operator and if-else
  • Iterative in Constraint Blocks (foreach constraints)
  • Disable Constraint
  • Static Constraints
  • In line Constraints
  • Functions in Constraints
  • Soft Constraints
  • Unique Constraints
  • Bidirectional Constraints
  • Solve-Before
• Random System Methods $urandom(), $random and $urandom_range();

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•  Blocking assignments
•  Non-Blocking assignments
•  Selection Statements
  •  Unique-If
  •  Priority-If
•  Loop Statements
  •  while, do-while
  •  foreach
  •  enhanced for loop
  •  repeat, forever
•  Jump Statements
  •  break
  •  continue
•  Named Blocks and Statement Labels
•  disable block and disable statements
  •  Event Control

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Randomize Queue SystemVerilog

In most of the queue use cases, queue is used as buffer or temporary storage. so there wont be much need to randomize queue.

randomize queue size

In below example, queue size will get randomized based on size constraint, and queue elements will get random values

1. Declare queue with rand
2. On randomization queue will get random values

class queue_rand;
  rand bit [7:0] qu[$];
  
  constraint size_c  { qu.size() inside {[4:10]}; }
  
  function void display();
    $display("qu size is = %0d",qu.size());
    $display("qu = %p",qu);
  endfunction
endclass

program queue_randomization;
  queue_rand pkt;

  initial begin
    pkt = new();
    pkt.randomize();
    pkt.display();   
  end
endprogram 

Simulator Output

qu size is = 7
qu = '{'h88, 'h9b, 'h9a, 'h10, 'h5f, 'hde, 'h84}

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