SystemVerilog Data Types
Table of Contents
Structural Data Types
wire and reg
structural data types called nets, which model hardware connections between circuit components. The wire nets act like real wires in circuits. The reg type holds their values until another value is put on them, just like a register hardware component.
The declarations for wire and reg signals are inside a module but outside any initial or always block.
The initial state of a,
reg is x unknown, wire is z.
Behavioral Data Types
integer, real, and time
An integer declares one or more variables of type integer. These variables can hold values ranging from -2^31 to (2^31)-1.
Integer Syntax:
integer integer_variable_name;
A real declaration declares one or more variables of type real. The real variables are stored as 64-bit quantities, and store the real values. Real numbers can be specified in either decimal notation (for example, 14.72) or in scientific notation (for example, 39e8).
Examples:
1.8 635.16
1.2E12 (the exponent symbol can be e or E)
1.30e-2
Syntax
real real_variable_name;
Default value of integer type variable is “x” and Default value of real type variable is “0”.
Examples:
integer a[0:64] ; // an array of 65 integer values
real float_v ; // a variable to store real value
Time
Time is a 64-bit quantity that can be used in conjunction with the $time system task to hold simulation time. Time is not supported for synthesis and hence is used only for simulation purposes.
Syntax
time time_variable_name;
Parameters
Parameters represent constants, hence it is illegal to modify their value at runtime. However, parameters can be modified at compilation time to have values that are different from those specified in the declaration assignment. This allows the customization of module instances. A parameter can be modified with the defparam statement, or in the module instance statement.
parameter size = 16 ;
logic
logic is the improved version of reg form Verilog to SystemVerilog, so it Can be driven by continuous assignments, gates, and modules in addition to being a variable. declaration:
bit – Unsigned
byte, shortint, int, longint – Signed
unsigned two-state types,
bit single_bit ; // unsigned single bit
bit [31:0] 32_bit ; // 32-bit unsigned integer
signed two-state types,
int integer; // 32-bit signed integer
byte 8_bit ; // 8-bit signed integer
shortint 16_bit ; // 16-bit signed integer
longint 64_bit ; // 64-bit signed integer
unsigned from signed two-state types,
int unsigned integer; // 32-bit unsigned integer
byte unsigned 8_bit; // 8-bit unsigned integer
shortint unsigned 16_bit; // 16-bit unsigned integer
longint unsigned 64_bit; // 64-bit unsigned integer
Void Data Types
The void data type represents non-existent data. This type can be specified as the return type of functions, indicating no return value.
syntax:
void’(function_call());
String
A string data type is variable size, it is a dynamically allocated array of bytes.
string declaration examples:
string s1 = "Hellow World";
string s2 = {"Hi"," ",s1};
bit [31:0] b = 128;
string s3 = b; // sets 128 to s3
module string_datatype;
//declaration
string s1 = "Hello World";
string s2 = {"Hi,"," ",s1};
bit[31:0]b= 128;
string s3 = b; // sets 128 to s3
initial begin
//display values
$display("String 1 s1 = %0s",s1);
$display("String 2 s2 = %0s",s2);
$display("String 3 s3 = %0d bit b = %0d",s3,b);
end
endmodule
Simulator Output
String 1 s1 = Hello World String 2 s2 = Hi, Hello World String 3 s3 = 128 bit b = 128
EVENT
SystemVerilog enhances the Verilog event in several ways. An event is now a handle to a synchronization object that can be passed around to routines. In Verilog, if the triggerin
g thread executes before the blocking thread, the trigger is missed. SystemVerilog introduces triggered function that lets you check whether an event has been triggered.
event declaration examples,
event e1;
event e2;
event done;
A detailed explanation of events and Event operations are explained in later chapters(SystemVerilog Events).
User Defined
The user can define a new type using typedef, as in C. This can then be instantiated as,
integer_v var1;
integer_v var2;