SystemVerilog struct and array difference

• Array groups the elements of same data type
• Struct groups the elements of different data type

Array


Collection of variables of same data type.

  int        addr[10]; //Array of int type          
  bit [31:0] data[63];  //Array of bit type 

Struct

Collection of variables of different data types.

  typedef enum logic {INVALID_PKT,VALID_PKT} pkt_type;
  
  typedef struct packed {
    byte       addr;
    pkt_type   valid;
    bit [31:0] data; 
  } mem_pkt; 

For detailed description refer to,

• SystemVerilog Struct
• SystemVerilog Arrays