SystemVerilog enum of logic bit int

SystemVerilog enum of logic bit int

This section provides the examples to declare SystemVerilog enum of logic type, enum of bit type and  enum of int type

enum of logic type example

module enum_datatype;
  //declaration
  enum logic [3:0] { red=0, green=1, blue=4, yellow, white=6, black=9 } Colors;
  
  initial begin
    Colors = Colors.first;
    for(int i=0;i < 6;i++) begin
      $display("Colors  ::  Value of %0s is \t= %0d",Colors.name(),Colors);
      Colors = Colors.next;
    end
  end
endmodule

Simulator Output

Colors :: Value of red is = 0
Colors :: Value of green is = 1
Colors :: Value of blue is = 4
Colors :: Value of yellow is = 5
Colors :: Value of white is = 6
Colors :: Value of black is = 9

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enum of bit type example

module enum_datatype;
  //declaration
  enum bit [3:0] { red=0, green=1, blue=4, yellow, white=6, black=9 } Colors;
  
  initial begin
    Colors = Colors.first;
    for(int i=0;i < 6;i++) begin
      $display("Colors  ::  Value of %0s is \t= %0d",Colors.name(),Colors);
      Colors = Colors.next;
    end
  end
endmodule

Simulator Output

Colors :: Value of red is = 0
Colors :: Value of green is = 1
Colors :: Value of blue is = 4
Colors :: Value of yellow is = 5
Colors :: Value of white is = 6
Colors :: Value of black is = 9

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enum of int type example

module enum_datatype;
  //declaration
  enum int { red=0, green=1, blue=4, yellow, white=6, black=9 } Colors;
  
  initial begin
    Colors = Colors.first;
    for(int i=0;i < 6;i++) begin
      $display("Colors  ::  Value of %0s is \t= %0d",Colors.name(),Colors);
      Colors = Colors.next;
    end
  end
endmodule

Simulator Output

Colors :: Value of red is = 0
Colors :: Value of green is = 1
Colors :: Value of blue is = 4
Colors :: Value of yellow is = 5
Colors :: Value of white is = 6
Colors :: Value of black is = 9

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