event control

Any change in a variable or net can be detected using the @ event control.

A change of any bits of a multi-bit variable shall trigger the event control. SystemVerilog adds an iff qualifier to the @ event control.

event control example

In the below example,
always block will get executed at any change in variables value within the always block.

module event_ctrl;
  bit [2:0] a,b;

  //always block will be executed at any value change in a and b
  always @(*)
  begin
    $display($time,"\tValue of a=%0d, b=%0d",a,b);
  end

  initial begin
    #2 a=5;
    #3 b=2;
    #2 a=1;
    #1 b=7;
    #2;
    $finish;
  end
endmodule

Simulator Output

2 Value of a=5, b=0
5 Value of a=5, b=2
7 Value of a=1, b=2
8 Value of a=1, b=7
$finish called from file "testbench.sv", line 27.
$finish at simulation time 10

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event control example 2

In below example,
always block will be executed at every posedge of the clk signal.

module event_ctrl;
  bit clk;
  always #2 clk = ~clk;

  //always block will be executed at every posedge of clk signal
  always @(posedge clk)
  begin
    $display($time,"\tInside always block");
  end

  initial begin
    #20 $finish;
  end
endmodule

Simulator Output

2 Inside always block
6 Inside always block
10 Inside always block
14 Inside always block
18 Inside always block
$finish called from file "testbench.sv", line 24.
$finish at simulation time 20

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event control example 3

In below example,
always block will be executed at every negedge of the clk signal.

module event_ctrl;
  bit clk;
  always #2 clk = ~clk;

  //always block will be executed at every negedge of clk signal
  always @(negedge clk)
  begin
    $display($time,"\tInside always block");
  end

  initial begin
    #20 $finish;
  end
endmodule

Simulator Output

4 Inside always block
8 Inside always block
12 Inside always block
16 Inside always block
$finish called from file "testbench.sv", line 24.
$finish at simulation time 20

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iff in event control example

In the below example,
block-1 will be executed at the posedge of clk if reset is equals to ‘0’.
block-2 will be executed at every posedge and negedge of the clk signal.

module event_ctrl;
  bit clk;
  bit reset;
  always #2 clk = ~clk;

  //at posedge of clk if reset is equals to '0',always block will be executed
  always @(posedge clk iff reset == 0)
  begin :block-1
    $display($time,"\tInside always block");
  end :block-1

  //always block will be executed at every posedge and negedge of clk signal
  always @(posedge reset or negedge reset)
  begin :block-2
    $display($time,"\tReset Value = %0d",reset);
  end :block-2

  initial begin
   #40 $finish;
  end
  initial begin
    reset = 1;
    #7 reset = 0;
    #8 reset = 1;
    #5 reset = 0;
  end
endmodule

Simulator Output

0 Reset Value = 1
7 Reset Value = 0
10 Inside always block
14 Inside always block
15 Reset Value = 1
20 Reset Value = 0
22 Inside always block
26 Inside always block
30 Inside always block
34 Inside always block
38 Inside always block
$finish called from file "testbench.sv", line 33.
$finish at simulation time 40

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