SystemVerilog Functions

functions

A Function can contain declarations of range, returned type, parameters, input arguments, registers, and events.

  • A function without a range or return type declaration returns a one-bit value
  • Any expression can be used as a function call argument
  • Functions cannot contain any time-controlled statements, and they cannot enable tasks
  • Functions can return only one value

SystemVerilog function can be,

  • static
  • automatic

Static Function

Static functions share the same storage space for all function calls.

Automatic Function

Automatic functions allocate unique, stacked storage for each function call.

SystemVerilog allows,

  • to declare an automatic variable in static functions
  • to declare the static variable in automatic functions
  • more capabilities for declaring function ports
  • multiple statements within a function without requiring a begin…end or fork…join block
  • returning from the function before reaching the end of the function
  • Passing values by reference, value, names, and position
  • default argument values
  • function output and inout ports
  • the default direction of argument is input if no direction has been specified.
  • default arguments type is logic if no type has been specified.

function examples

function arguments in parentheses

module sv_function;
  int x;
  //function to add two integer numbers.
  function int sum(input int a,b);
    sum = a+b;   
  endfunction

  initial begin
    x=sum(10,5);
    $display("\tValue of x = %0d",x);
  end
endmodule

Simulator Output

Value of x=15

Click to execute on

function arguments in declarations and mentioning directions

module sv_function;
  int x;

  //function to add two integer numbers.
  function int sum;
    input int a,b;
    sum = a+b;   
  endfunction
  initial begin
    x=sum(10,5);
    $display("\tValue of x = %0d",x);
  end
endmodule

Simulator Output

Value of x = 15

Click to execute on

function with return value with the return keyword

In the below example,
arguments in declarations and directions, return value is specified using the return statement.

module sv_function;
  int x;

  //function to add two integer numbers.
  function int sum;
    input int a,b;
    return a+b;   
  endfunction

  initial begin
    x=sum(10,5);
    $display("\tValue of x = %0d",x);
  end
endmodule

Simulator Output

Value of x = 15

Click to execute on

Void function

The example below shows usage of void function, void function,(function with no return value)

module sv_function;
  int x;
  //void function to display current simulation time 
  function void current_time;
    $display("\tCurrent simulation time is %0d",$time);    
  endfunction
 
  initial begin
    #10;
    current_time();
    #20;
    current_time();
  end
endmodule

Simulator Output

Current simulation time is 10
Current simulation time is 30

Click to execute on

discarding function return value

The function return value must be assigned to a variable or used in an expression.

Calling a function without return value assigned to a variable can result in a warning message. SystemVerilog void data type is used to discard a function’s return value without any warning message.

module sv_function;
  int x;
   //function to add two integer numbers. 
  function int sum;
    input int a,b;
    return a+b;    
  endfunction
 
  initial begin
    $display("Calling function with void");
    void'(sum(10,5));
  end
 endmodule

Simulator Output

Calling function with void

Click to execute on

function call as an expression

module sv_function;
  int x;
  //function to add two integer numbers. 
  function int sum;
    input int a,b;
  return a+b;    
  endfunction
  initial begin
    x = 10 + sum(10,5);
    $display("\tValue of x = %0d",x);
  end
endmodule

Simulator Output

Value of x = 25

Click to execute on

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