Register defines
Table of Contents
UVM register library has the defines declared in it. these are being used in the RAL model base classes, user can override these defines.
uvm_reg_defines are,
- `UVM_REG_ADDR_WIDTH
- `UVM_REG_DATA_WIDTH
- `UVM_REG_BYTENABLE_WIDTH
- `UVM_REG_CVR_WIDTH
UVM_REG_ADDR_WIDTH
- Maximum address width in bits
Default value is 64 - Used to define the uvm_reg_addr_t type
UVM_REG_DATA_WIDTH
- Maximum data width in bits
Default value is 64 - Used to define the uvm_reg_data_t type
UVM_REG_BYTENABLE_WIDTH
- Maximum number of byte enable bits
- Default value is one per byte in `UVM_REG_DATA_WIDTH
- Used to define the
uvm_reg_byte_en_t type
UVM_REG_CVR_WIDTH
- Maximum number of bits in a uvm_reg_cvr_t coverage model set
- Default value is 32
