Connecting TLM Port export imp port
Table of Contents
In the previous examples, we have seen connecting the port to the imp port.This example shows connecting TLM Port -> Export -> Imp_port.
TLM TesetBench Components are,
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Name Type
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uvm_test_top basic_test
env environment
comp_a component_a
trans_out uvm_blocking_put_port
comp_b component_b
sub_comp_b_a sub_component_b_a
trans_in uvm_blocking_put_imp
trans_in uvm_blocking_put_export
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Implement TLM port in comp_a
Implementing TLM port in comp_a involves below steps,
- Declare the uvm_blocking_put_port
- Create the port
- Randomize the transaction class
- Send the transaction to the comp_b through put() method
class component_a extends uvm_component; //Step-1. Declaring blocking port uvm_blocking_put_port #(transaction) trans_out; `uvm_component_utils(component_a) //--------------------------------------- // Constructor //--------------------------------------- function new(string name, uvm_component parent); super.new(name, parent); trans_out = new("trans_out", this); //Step-2. Creating the port endfunction : new //--------------------------------------- // run_phase //--------------------------------------- virtual task run_phase(uvm_phase phase); phase.raise_objection(this); trans = transaction::type_id::create("trans", this); void'(trans.randomize()); //Step-3. randomizing the transction `uvm_info(get_type_name(),$sformatf(" tranaction randomized"),UVM_LOW) `uvm_info(get_type_name(),$sformatf(" Printing trans, \n %s",trans.sprint()),UVM_LOW) `uvm_info(get_type_name(),$sformatf(" Before calling port put method"),UVM_LOW) trans_out.put(trans); //Step-4. Sending trans through port put method `uvm_info(get_type_name(),$sformatf(" After calling port put method"),UVM_LOW) phase.drop_objection(this); endtask : run_phaseendclass : component_a |
Implement TLM port in sub_comp_b_a
Implementing TLM port in sub_comp_b_a involves below steps,
- Declare the uvm_blocking_put_imp
- Create the imp port
- Implement the put() method to receive the transaction
class sub_component_b_a extends uvm_component; transaction trans; //Step-1. Declaring blocking imp port uvm_blocking_put_imp#(transaction,sub_component_b_a) trans_in; `uvm_component_utils(sub_component_b_a) //--------------------------------------- // Constructor //--------------------------------------- function new(string name, uvm_component parent); super.new(name, parent); trans_in = new("trans_in", this); //Step-2. Creating imp port endfunction : new //--------------------------------------- // Imp port put method //--------------------------------------- //Step-3. Implementing imp port virtual task put(transaction trans); `uvm_info(get_type_name(),$sformatf(" Recived trans On IMP Port"),UVM_LOW) `uvm_info(get_type_name(),$sformatf(" Printing trans, \n %s",trans.sprint()),UVM_LOW) endtaskendclass : sub_component_b_a |
Implement TLM port in comp_b
Implementing TLM port in comp_b involves below steps,
- Declare the uvm_blocking_put_export
- Create the export
- Connect export to the imp port
class component_b extends uvm_component; sub_component_b_a sub_comp_b_a; //Step-1. Declaring blocking export uvm_blocking_put_export#(transaction) trans_in; `uvm_component_utils(component_b) //--------------------------------------- // Constructor //--------------------------------------- function new(string name, uvm_component parent); super.new(name, parent); trans_in = new("trans_in", this); //Step-2. Creating export endfunction : new //--------------------------------------- // build_phase - Create the components //--------------------------------------- function void build_phase(uvm_phase phase); super.build_phase(phase); sub_comp_b_a = sub_component_b_a::type_id::create("sub_comp_b_a", this); endfunction : build_phase //--------------------------------------- // Connect_phase //--------------------------------------- function void connect_phase(uvm_phase phase); trans_in.connect(sub_comp_b_a.trans_in); //Step-3. Connecting export to the imp port endfunction : connect_phaseendclass : component_b |
Environment code
In the environment file comp_a port is connected with the comp_b export.
function void connect_phase(uvm_phase phase); comp_a.trans_out.connect(comp_b.trans_in); //Connecting port with export endfunction : connect_phase |
Simulator Output
UVM_INFO @ 0: reporter [RNTST] Running test basic_test... -------------------------------------------------------- Name Type Size Value -------------------------------------------------------- uvm_test_top basic_test - @1842 env environment - @1911 comp_a component_a - @1943 trans_out uvm_blocking_put_port - @1978 comp_b component_b - @2011 sub_comp_b_a sub_component_b_a - @2080 trans_in uvm_blocking_put_imp - @2115 trans_in uvm_blocking_put_export - @2046 -------------------------------------------------------- UVM_INFO component_a.sv(29) @ 0: uvm_test_top.env.comp_a [component_a] tranaction randomized UVM_INFO component_a.sv(30) @ 0: uvm_test_top.env.comp_a [component_a] Printing trans, --------------------------------- Name Type Size Value --------------------------------- trans transaction - @2157 addr integral 4 'he wr_rd integral 1 'h0 wdata integral 8 'h4 --------------------------------- UVM_INFO component_a.sv(32) @ 0: uvm_test_top.env.comp_a [component_a] Before calling port put method UVM_INFO sub_component_b_a.sv(24) @ 0: uvm_test_top.env.comp_b.sub_comp_b_a [sub_component_b_a] Recived trans On IMP Port UVM_INFO sub_component_b_a.sv(26) @ 0: uvm_test_top.env.comp_b.sub_comp_b_a [sub_component_b_a] Printing trans, --------------------------------- Name Type Size Value --------------------------------- trans transaction - @2157 addr integral 4 'he wr_rd integral 1 'h0 wdata integral 8 'h4 --------------------------------- UVM_INFO component_a.sv(34) @ 0: uvm_test_top.env.comp_a [component_a] After calling port put method UVM_INFO /playground_lib/uvm-1.2/src/base/uvm_objection.svh(1271) @ 0: reporter [TEST_DONE] UVM_INFO /playground_lib/uvm-1.2/src/base/uvm_report_server.svh(847) @ 0: reporter [UVM/REPORT/SERVER]
