Skip to content

Verification Guide

  • SystemVerilog
  • UVM
  • SystemC
  • Interview Questions
  • Quiz
  • SystemVerilog
  • UVM
  • SystemC
  • Interview Questions
  • Quiz

Verilog Example Codes

  • Inverter
  • Buffer
  • Transmission Gate
  • TriState Buffer
  • Basic and Universal Gates
  • Flip Flops
    • SR Flip Flop
    • JK  Flip Flop
    • D   Flip Flop
    • T    Flip Flop
    • Master-Slave (MS) Flip Flop
  • Serial Adder
  • Counters
    • 4-bit Synchronous Counter
    • 4-bit Asynchronous Counter
  • Adders
    • 8-bit Carry ripple adder
    • 8-bit Carry Look-Ahead adder
    • 8-bit Carry skip adder
    • 4-bit BCD adder and Subs-tractor
  • Multipliers
    • 4×4 Unsigned array Multiplier
    • 4×4 Booth Multiplier
  • Comparator’s
    • 4-bit magnitude comparator
    • 4-bit LFSR
    • 4-bit Parity Generator
    • 4-bit Universal Shift Register
  • FSM to detect sequence 1110
    • Melay with Overlap
    • Melay without Overlap 
    • Moore with Overlap
    • Moore without Overlap 
  • FIFO buffer
  • LIFO buffer
  • 3-bit Arbiter
  • SystemVerilog
  • UVM
  • SystemC
  • Interview Questions
  • Quiz
  • SystemVerilog
  • UVM
  • SystemC
  • Interview Questions
  • Quiz
Verification Guide Proudly powered by WordPress
We use cookies to ensure that we give you the best experience on our website. If you continue to use this site we will assume that you are happy with it.Ok
x