Tasks and Functions provide a means of splitting code into small parts.
A Task can contain a declaration of parameters, input arguments, output arguments, in-out arguments, registers, events, and zero or more behavioral statements.
SystemVerilog task can be,
static
automatic
Static tasks
Static tasks share the same storage space for all task calls.
Automatic tasks
Automatic tasks allocate unique, stacked storage for each task call.
SystemVerilog allows,
to declare an automatic variable in a static task
to declare a static variable in an automatic task
more capabilities for declaring task ports
multiple statements within task without requiring a begin…end or fork…join block
returning from the task before reaching the end of the task
passing values by reference, value, names, and position
default argument values
the default direction of argument is input if no direction has been specified
default arguments type is logic if no type has been specified
task examples
task arguments in parentheses
module sv_task;
int x;
//task to add two integer numbers.
task sum(input int a,b,output int c);
c = a+b;
endtask
initial begin
sum(10,5,x);
$display("\tValue of x = %0d",x);
end
endmodule
task arguments in declarations and mentioning directions
module sv_task;
int x;
//task to add two integer numbers.
task sum;
input int a,b;
output int c;
c = a+b;
endtask
initial begin
sum(10,5,x);
$display("\tValue of x = %0d",x);
end
endmodule
disable fork; causes the process to kill/terminate all the active processes started from fork blocks.
disable fork example
In the below example,
On execution of the disable fork, all the active process will get terminated.
Process-2 of fork-1, Process-1, and Process-2 of fork-2 will get terminated.
module disable_fork;
initial begin
$display("-----------------------------------------------------------------");
//fork-1
fork
//Process-1
begin
$display($time,"\tProcess-1 of fork-1 Started");
#5;
$display($time,"\tProcess-1 of fork-1 Finished");
end
//Process-2
begin
$display($time,"\tProcess-2 of fork-1 Started");
#20;
$display($time,"\tProcess-2 of fork-1 Finished");
end
join_any
//fork-2
fork
//Process-1
begin
$display($time,"\tProcess-1 of fork-2 Started");
#5;
$display($time,"\tProcess-1 of fork-2 Finished");
end
//Process-2
begin
$display($time,"\tProcess-2 of fork-2 Started");
#20;
$display($time,"\tProcess-2 of fork-2 Finished");
end
join_none
disable fork;
$display("-----------------------------------------------------------------");
$display($time,"\tAfter disable-fork");
$display("-----------------------------------------------------------------");
end
endmodule
Simulator Output
-----------------------------------------------------------------
0 Process-1 of fork-1 Started
0 Process-2 of fork-1 Started
5 Process-1 of fork-1 Finished
-----------------------------------------------------------------
5 After disable-fork
-----------------------------------------------------------------
sub_process started from process-2 will get terminated during the execution of disable fork.
module disable_fork;
initial begin
$display("-----------------------------------------------------------------");
fork
//Process-1
begin
$display($time,"\tProcess-1 of fork-1 Started");
#5;
$display($time,"\tProcess-1 of fork-1 Finished");
end
//Process-2
begin
sub_process();
end
join_any
disable fork;
$display("-----------------------------------------------------------------");
$display($time,"\tAfter disable-fork");
$display("-----------------------------------------------------------------");
end
//Sub-Process
task sub_process;
$display($time,"\tSub-Process Started");
#10;
$display($time,"\tSub-Process Finished");
endtask
endmodule
Simulator Output
-----------------------------------------------------------------
0 Process-1 of fork-1 Started
0 Sub-Process Started
5 Process-1 of fork-1 Finished
-----------------------------------------------------------------
5 After disable-fork
-----------------------------------------------------------------
wait fork; causes the process to block until the completion of all processes started from fork blocks.
wait fork example
In the below example,
after the completion of Process-1 (i.e, after 5ns) fork-join_any will get unblocked, the $finish will get called and it ends the simulation.
The simulation will get ended in the middle of the execution of process-2, this can be avoided with the use of wait-fork.
The problem in this example is overcome in example-2 with the use of wait fork;
module wait_fork;
initial begin
$display("-----------------------------------------------------------------");
fork
//Process-1
begin
$display($time,"\tProcess-1 Started");
#5;
$display($time,"\tProcess-1 Finished");
end
//Process-2
begin
$display($time,"\tProcess-2 Started");
#20;
$display($time,"\tProcess-2 Finished");
end
join_any
$display("-----------------------------------------------------------------");
$finish; //ends the simulation
end
endmodule
Simulator Output
-----------------------------------------------------------------
0 Process-1 Started
0 Process-2 Started
5 Process-1 Finished
-----------------------------------------------------------------
wait fork will wait for the completion of the second thread in the fork-join_any.
for better understanding compare the result of Example-1 and Example-2
module wait_fork;
initial begin
$display("-----------------------------------------------------------------");
fork
//Process-1
begin
$display($time,"\tProcess-1 Started");
#5;
$display($time,"\tProcess-1 Finished");
end
//Process-2
begin
$display($time,"\tProcess-2 Started");
#20;
$display($time,"\tProcess-2 Finished");
end
join_any
wait fork; //waiting for the completion of active fork threads
$display("-----------------------------------------------------------------");
$finish; //ends the simulation
end
endmodule
Simulator Output
-----------------------------------------------------------------
0 Process-1 Started
0 Process-2 Started
5 Process-1 Finished
20 Process-2 Finished
-----------------------------------------------------------------
As in the case of Fork-Join and Fork-Join_any fork block is blocking, but in case of Fork-Join_none fork block will be non-blocking.
Processes inside the fork-join_none block will be started at the same time, fork block will not wait for the completion of the Process inside the fork-join_none.
SystemVerilog Fork Join none
fork join none example
In the below example,
The fork will start Process-1 and Process-2 at the same time, and it will come out of the block. Process-1 and Process-2 will be executed until the completion.
module fork_join_none;
initial begin
$display("-----------------------------------------------------------------");
fork
//Process-1
begin
$display($time,"\tProcess-1 Started");
#5;
$display($time,"\tProcess-1 Finished");
end
//Process-2
begin
$display($time,"\tProcess-2 Startedt");
#20;
$display($time,"\tProcess-2 Finished");
end
join_none
$display($time,"\tOutside Fork-Join_none");
$display("-----------------------------------------------------------------");
end
endmodule
Fork-Join_any will be unblocked after the completion of any of the Processes.
SystemVerilog Fork Join any
fork join any example
In the below example,
fork block will be blocked until the completion of any of the Process Process-1 or Process-2.
Both Process-1 and Process-2 will start at the same time, Process-1 will finish at 5ns and Process-2 will finish at 20ns. fork-join_any will be unblocked at 5ns.
module fork_join;
initial begin
$display("-----------------------------------------------------------------");
fork
//Process-1
begin
$display($time,"\tProcess-1 Started");
#5;
$display($time,"\tProcess-1 Finished");
end
//Process-2
begin
$display($time,"\tProcess-2 Started");
#20;
$display($time,"\tProcess-2 Finished");
end
join_any
$display($time,"\tOutside Fork-Join");
$display("-----------------------------------------------------------------");
end
endmodule
Simulator Output
--------------------------------------------------------
0 Thread-1 Started
0 Thread-2 Started
5 Thread-1 Finished
5 Outside Fork-Join
-----------------------------------------------------------------
20 Process-2 Finished
Fork-Join will start all the processes inside it parallel and wait for the completion of all the processes.
SystemVerilog Fork Join
fork join example
In below example,
fork block will be blocked until the completion of process-1 and Process-2.
Both process-1 and Process-2 will start at the same time, Process-1 will finish at 5ns and Process-2 will finish at 20ns. fork-join will be unblocked at 20ns.
module fork_join;
initial begin
$display("-----------------------------------------------------------------");
fork
//-------------------
//Process-1
//-------------------
begin
$display($time,"\tProcess-1 Started");
#5;
$display($time,"\tProcess-1 Finished");
end
//-------------------
//Process-2
//-------------------
begin
$display($time,"\tProcess-2 Started");
#20;
$display($time,"\tProcess-2 Finished");
end
join
$display($time,"\tOutside Fork-Join");
$display("-----------------------------------------------------------------");
$finish;
end
endmodule
Any change in a variable or net can be detected using the @ event control.
A change of any bits of a multi-bit variable shall trigger the event control. SystemVerilog adds an iff qualifier to the @ event control.
event control example
In the below example,
always block will get executed at any change in variables value within the always block.
module event_ctrl;
bit [2:0] a,b;
//always block will be executed at any value change in a and b
always @(*)
begin
$display($time,"\tValue of a=%0d, b=%0d",a,b);
end
initial begin
#2 a=5;
#3 b=2;
#2 a=1;
#1 b=7;
#2;
$finish;
end
endmodule
Simulator Output
2 Value of a=5, b=0
5 Value of a=5, b=2
7 Value of a=1, b=2
8 Value of a=1, b=7
$finish called from file "testbench.sv", line 27.
$finish at simulation time 10
In below example,
always block will be executed at every posedge of the clk signal.
module event_ctrl;
bit clk;
always #2 clk = ~clk;
//always block will be executed at every posedge of clk signal
always @(posedge clk)
begin
$display($time,"\tInside always block");
end
initial begin
#20 $finish;
end
endmodule
Simulator Output
2 Inside always block
6 Inside always block
10 Inside always block
14 Inside always block
18 Inside always block
$finish called from file "testbench.sv", line 24.
$finish at simulation time 20
In below example,
always block will be executed at every negedge of the clk signal.
module event_ctrl;
bit clk;
always #2 clk = ~clk;
//always block will be executed at every negedge of clk signal
always @(negedge clk)
begin
$display($time,"\tInside always block");
end
initial begin
#20 $finish;
end
endmodule
Simulator Output
4 Inside always block
8 Inside always block
12 Inside always block
16 Inside always block
$finish called from file "testbench.sv", line 24.
$finish at simulation time 20
In the below example,
block-1 will be executed at the posedge of clk if reset is equals to ‘0’.
block-2 will be executed at every posedge and negedge of the clk signal.
module event_ctrl;
bit clk;
bit reset;
always #2 clk = ~clk;
//at posedge of clk if reset is equals to '0',always block will be executed
always @(posedge clk iff reset == 0)
begin :block-1
$display($time,"\tInside always block");
end :block-1
//always block will be executed at every posedge and negedge of clk signal
always @(posedge reset or negedge reset)
begin :block-2
$display($time,"\tReset Value = %0d",reset);
end :block-2
initial begin
#40 $finish;
end
initial begin
reset = 1;
#7 reset = 0;
#8 reset = 1;
#5 reset = 0;
end
endmodule
Simulator Output
0 Reset Value = 1
7 Reset Value = 0
10 Inside always block
14 Inside always block
15 Reset Value = 1
20 Reset Value = 0
22 Inside always block
26 Inside always block
30 Inside always block
34 Inside always block
38 Inside always block
$finish called from file "testbench.sv", line 33.
$finish at simulation time 40
The execution of a break statement leads to the end of the loop.
break shall be used in all the loop constructs (while, do-while, foreach, for, repeat and forever).
syntax
break;
break in while loop
module break_in_while_loop;
int i;
initial begin
$display("-----------------------------------------------------------------");
i = 8;
while(i!=0) begin
$display("\tValue of i=%0d",i);
if(i == 4) begin
$display("\tCalling break,");
break;
end
i--;
end
$display("-----------------------------------------------------------------");
end
endmodule
Simulator Output
-----------------------------------------------------------------
Value of i=8
Value of i=7
Value of i=6
Value of i=5
Value of i=4
Calling break,
-----------------------------------------------------------------
module break_in_do_while_loop;
int i;
initial begin
$display("-----------------------------------------------------------------");
i = 8;
do begin
$display("\tValue of i=%0d",i);
if(i == 4) begin
$display("\tCalling break,");
break;
end
i--;
end
while(i!=0);
$display("-----------------------------------------------------------------");
end
endmodule
Simulator Output
-----------------------------------------------------------------
Value of i=8
Value of i=7
Value of i=6
Value of i=5
Value of i=4
Calling break,
-----------------------------------------------------------------
module foreach_loop_break;
int a[4];
initial begin
$display("-----------------------------------------------------------------");
foreach(a[i]) a[i] = i;
foreach(a[i]) begin
$display("\tValue of a[%0d]=%0d",i,a[i]);
if(i == 2) begin
$display("\tCalling break,");
break;
end
end
$display("-----------------------------------------------------------------");
end
endmodule
Simulator Output
-----------------------------------------------------------------
Value of a[0]=0
Value of a[1]=1
Value of a[2]=2
Calling break,
-----------------------------------------------------------------
In below example,
when the loop value equals 4, the break is called this leads to the end of the loop.
module break_in_loop;
initial begin
$display("-----------------------------------------------------------------");
for(int i=0;i<8;i++) begin
$display("\tValue of i=%0d",i);
if(i == 4) begin
$display("\tCalling break,");
break;
end
end
$display("-----------------------------------------------------------------");
end
endmodule
Simulator Output
-----------------------------------------------------------------
Value of i=0
Value of i=1
Value of i=2
Value of i=3
Value of i=4
Calling break,
-----------------------------------------------------------------
module repeat_loop_break;
int i;
initial begin
$display("-----------------------------------------------------------------");
repeat(5) begin
$display("\tValue of i=%0d",i);
if(i == 2) begin
$display("\tCalling break,");
break;
end
i++;
end
$display("-----------------------------------------------------------------");
end
endmodule
Simulator Output
-----------------------------------------------------------------
Value of i=0
Value of i=1
Value of i=2
Calling break,
-----------------------------------------------------------------
module forever_loop_break;
int i;
initial begin
$display("-----------------------------------------------------------------");
i = 5;
forever begin
$display("\tValue of i=%0d",i);
if(i == 2) begin
$display("\tCalling break,");
break;
end
i++;
end
$display("-----------------------------------------------------------------");
end
endmodule
Simulator Output
-----------------------------------------------------------------
Value of i=0
Value of i=1
Value of i=2
Calling break,
-----------------------------------------------------------------
Execution of continue statement leads to skip the execution of statements followed by continue and jump to next loop or iteration value.
syntax
continue;
Continue example
In below example,
when ever the loop value is with in 3 to 6, continue statement will be executed, this leads to skip the execution of display statement after the continue.
module continue_in_loop;
initial begin
$display("-----------------------------------------------------------------");
for(int i=0;i<8;i++) begin
if((i > 2) && (i < 7))begin
$display("\t\tCalling continue,");
continue;
end
$display("\t\tAfter Continue\t:: Value of i=%0d",i);
end
$display("-----------------------------------------------------------------");
end
endmodule
Simulator Output
-----------------------------------------------------------------
After Continue :: Value of i=0
After Continue :: Value of i=1
After Continue :: Value of i=2
Calling continue,
Calling continue,
Calling continue,
Calling continue,
After Continue :: Value of i=7
-----------------------------------------------------------------
repeat will execute the statements within the loop for a loop variable number of times.
if the loop variable is N, then the statements within the repeat block will be executed N number of times.
repeat loop syntax
repeat(<variable>) begin
//statement - 1
...
//statement - n
end
statements 1-n will be executed for a variable value number of times.
repeat loop example
In the below example,
repeat loop value is 4, so the statements within the repeat loop will be executed for 4 times.
module repeat_loop;
int a;
initial begin
$display("-----------------------------------------------------------------");
repeat(4) begin
$display("\tValue of a=%0d",a);
a++;
end
$display("-----------------------------------------------------------------");
end
endmodule
Simulator Output
-----------------------------------------------------------------
Value of a=0
Value of a=1
Value of a=2
Value of a=3
-----------------------------------------------------------------
As the name says forever loop will execute the statements inside the loop forever.
It can be said as indefinite iteration.
forever loop syntax
forever begin
//statement - 1
...
//statement - n
end
forever loop example
module forever_loop;
int a;
initial begin
$display("-----------------------------------------------------------------");
forever begin
$display("\tValue of a=%0d",a);
a++;
#5;
end
$display("-----------------------------------------------------------------");
end
initial begin
#20 $finish;
end
endmodule
Simulator Output
-----------------------------------------------------------------
Value of a=0
Value of a=1
Value of a=2
Value of a=3
$finish called from file "testbench.sv", line 27.
$finish at simulation time 20
SystemVerilog for loop is enhanced for loop of Verilog.
In Verilog,
the control variable of the loop must be declared before the loop
allows only a single initial declaration and single step assignment within the for a loop
SystemVerilog for loop allows,
declaration of a loop variable within the for loop
one or more initial declaration or assignment within the for loop
one or more step assignment or modifier within the for loop
for loop syntax
for(initialization; condition; modifier) begin
//statement - 1
...
//statement - n
end
Initialization: executed first, and only once. This allows the user to declare and initialize loop control variables.
Condition: the condition is evaluated. If it is true, the body of the loop is executed, else the flow jumps to the statement after the ‘for’ loop.
Modifier: at the end of each iteration it will be executed, and execution moves to Condition.
for loop example
Below example shows the declaration of a loop variable within the for loop.
module for_loop;
initial begin
$display("-----------------------------------------------------------------");
for(int i=0;i<5;i++) $display("\t Value of i = %0d",i);
$display("-----------------------------------------------------------------");
end
endmodule
Simulator Output
-----------------------------------------------------------------
Value of i = 0
Value of i = 1
Value of i = 2
Value of i = 3
Value of i = 4
-----------------------------------------------------------------
Below example shows the declaration and initialization of two variables i and j in for loop.
module for_loop;
initial begin
$display("-----------------------------------------------------------------");
for ( int j=0,i=4;j<8;j++) begin
if(j==i) $display("\tValue j equals to Value of i. j=%0d i=%0d",j,i);
end
$display("-----------------------------------------------------------------");
end
endmodule
Simulator Output
-----------------------------------------------------------------
Value j=4 equals to Value of i=4
-----------------------------------------------------------------
Below example shows the use of two modifiers j++ and i– within the for loop.
module for_loop;
initial begin
$display("-----------------------------------------------------------------");
for ( int j=0,i=7;j<8;j++,i--) begin
$display("\tValue j=%0d Value of i=%0d",j,i);
end
$display("-----------------------------------------------------------------");
end
endmodule
Simulator Output
-----------------------------------------------------------------
Value j equals to Value of i. j=0 i=7
Value j equals to Value of i. j=1 i=6
Value j equals to Value of i. j=2 i=5
Value j equals to Value of i. j=3 i=4
Value j equals to Value of i. j=4 i=3
Value j equals to Value of i. j=5 i=2
Value j equals to Value of i. j=6 i=1
Value j equals to Value of i. j=7 i=0
-----------------------------------------------------------------
