SystemVerilog Virtual Interface

Virtual Interface

A virtual interface is a variable that represents an interface instance.

  • The virtual interface must be initialized before using it. i.e, Virtual interface must be connected/pointed to the actual interface
  • Accessing the uninitialized virtual interface result in a run-time fatal error
  • Virtual interfaces can be declared as class properties, which can be initialized procedural or by an argument to new()
  • The virtual interfaces can be passed as arguments to the tasks, functions, or methods
  • All the interface variables/Methods can be accessed via a virtual interface handle. i.e virtual_interface.variable
  • A single virtual interface variable can thus represent different interface instances at different times throughout the simulation

Only the following operations are directly allowed on virtual interface variables,

  • Assignment ( = ) to and Equality ( == ), inequality ( != ) with,
    • another virtual interface of the same type
    • an interface instance of the same type
    • the special constant null

What is the need for a virtual interface in SystemVerilog?

SystemVerilog interface is static in nature, whereas classes are dynamic in nature. because of this reason, it is not allowed to declare the interface within classes, but it is allowed to refer to or point to the interface. A virtual interface is a variable of an interface type that is used in classes to provide access to the interface signals.


virtual interface_name instance_name;

Virtual Interface example

The below example shows the declaration of a virtual interface, connecting the virtual interface to an interface, and accessing interface signals with a virtual interface handle.

Virtual Interface declaration

//virtual interface
virtual intf vif;

Connecting virtual interface with interface

function new(virtual intf vif);
  //get the interface from test
  this.vif = vif;

Accessing interface signal using a virtual interface handle

vif.a = 6;
vif.b = 4;
$display("Value of a = %0d, b = %0d",vif.a,vif.b);
$display("Sum of a and b, c = %0d",vif.c);

Complete env code

class environment;
  //virtual interface
  virtual intf vif;
  function new(virtual intf vif);
    //get the interface from test
    this.vif = vif;
  //run task
  task run;
    vif.a = 6;
    vif.b = 4;
    $display("Value of a = %0d, b = %0d",vif.a,vif.b);
    $display("Sum of a and b, c = %0d",vif.c);

TestCase Code

Testcase receives the interface handle from the testcase and passes it to env.

program test(intf i_intf);
  //declaring environment instance
  environment env;
  initial begin
    //creating environment
    env = new(i_intf);
    //calling run of env;

tbench_top Code

tbench_to is the top file, in which design instance, interface instance, and the test case is instantiated.

module tbench_top;
  //creatinng instance of interface
  intf i_intf();
  //Testcase instance
  test t1(i_intf);  
  //DUT instance, interface signals are connected to the DUT ports
  adder DUT (

Simulator Output

Value of a = 6, b = 4
Sum of a and b, c = 10

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