UVM Register Model Adapter
Table of Contents
With the UVM Register model, we do design register access, i.e WRITE to the design register or READ from the design register by calling RAL methods. Finally, these transactions have to be placed to design bus, this will be done by RAL component Adapter.
The RAL adapter acts as a converter between the RAL model and Interface. It converts transactions of RAL methods to Interface/Bus transactions.
- The Adapter converts between register model read, write methods and the interface-specific transactions
- The transaction adapter is implemented by extending the uvm_reg_adapter class and implementing the reg2bus() and bus2reg() methods
UVM RAL reg2bus
- reg2bus method converts the RAL transactions to Interface (bus) transactions
UVM RAL bus2reg
- bus2reg method converts the Interface (bus) transactions to RAL transactions
class tb_env extends uvm_env;
reg_model regmodel;
uvm_reg_predictor#(ahb_trans) ahb2reg_predictor;
reg2ahb_adapter reg_adapter;
ahb_agent ahb;
virtual function void build_phase(uvm_phase phase);
ahb2reg_predictor = new(“ahb2reg_predictor”, this);
endfunction
virtual function void connect_phase(uvm_phase phase);
if (regmodel.get_parent() == null) begin
reg_adapter = reg2ahb_adapter::type_id::create(“reg_adapter”,,get_full_name());
...
ahb2reg_predictor.map = regmodel.AHB;
ahb2reg_predictor.adapter = reg_adapter;
ahb.monitor.ap.connect(ahb2reg_predictor.bus_in);
end
...
endfunction
...
endclass