UVM Register Model Predictor
We know that the UVM Register model maintains the latest design register values in it. but how Register model will get to know the latest values?
This will be done by the UVM RAL component Predictor.
UVM RAL Predictor predicts the register access done through the register model and updates the RAL Model registers. UVM RAL provides the base class uvm_reg_predictor. uvm_reg_predictor updates the register model based on observed transactions published by a monitor.
- Any register access done through the register model is predicted and updated inherently by the base classes (implicit prediction)
- Prediction of the register values in the model can also be done explicitly using an external predictor which also takes care of interface bus transactions not occurring through the register model (explicit prediction)
- Implicit prediction only requires the integration of the register model with one or more bus sequencers
- Updates to the mirror are predicted automatically (i.e., implicitly) by the register model after the completion of each read, write, peek, or poke operation
- Explicit prediction requires the register model to be integrated with both the bus sequencers and corresponding bus monitors
- In this mode, the implicit prediction is turned off and all updates to the mirror are predicted externally (i.e., explicitly) by a uvm_reg_predictor component, one for each bus interface