Category: Verilog

Verilog Tutorial

Basic Concepts:Done:
1.Lexical conventions
2.1 Lexical tokens ……………………………………………………………………………………………………………… 6
2.2 White space…………………………………………………………………………………………………………………. 6
2.3 Comments …………………………………………………………………………………………………………………… 6
2.4 Operators…………………………………………………………………………………………………………………….. 6
2.5 Numbers……………………………………………………………………………………………………………………… 6
2.6 Strings ………………………………………………………………………………………………………………………. 10
System tasks and functions

Done:
3. Data types…………………………………………………………………………………………………………………………. 20
3.1 Value set……………………………………………………………………………………………………………………. 20
3.2 Nets and variables ………………………………………………………………………………………………………. 20
3.3 Vectors ……………………………………………………………………………………………………………………… 23
Variable Data Types in detail ( regs, Integers, reals, times, and realtimes)
3.10 Arrays……………………………………………………………………………………………………………………….. 33
3.11 Parameters…………………………………………………………………………………………………………………. 34

10. Tasks and functions………………………………………………………………………………………………………….. 151
10.1 Distinctions between tasks and functions …………………………………………………………………….. 151
10.2 Tasks and task enabling …………………………………………………………………………………………….. 151
10.3 Functions and function calling……………………………………………………………………………………. 156

12. Hierarchical structures ……………………………………………………………………………………………………… 165
12.1 Modules…………………………………………………………………………………………………………………… 165
12.2 Overriding module parameter values…………………………………………………………………………… 179
12.3 Ports ……………………………………………………………………………………………………………………….. 184
12.4 Hierarchical names …………………………………………………………………………………………………… 192
12.5 Upwards name referencing ………………………………………………………………………………………… 195
12.6 Scope rules ……………………………………………………………………………………………………………… 197

This can be done later
17. System tasks and functions ……………………………………………………………………………………………….. 277
17.1 Display system tasks …………………………………………………………………………………………………. 277
17.2 File input-output system tasks and functions………………………………………………………………… 286
17.3 Timescale system tasks ……………………………………………………………………………………………… 297
17.4 Simulation control system tasks………………………………………………………………………………….. 301
17.5 PLA modeling system tasks……………………………………………………………………………………….. 302
17.6 Stochastic analysis tasks ……………………………………………………………………………………………. 306
17.7 Simulation time system functions……………………………………………………………………………….. 308
17.8 Conversion functions ………………………………………………………………………………………………… 310
17.9 Probabilistic distribution functions ……………………………………………………………………………… 311
17.10 Command line input………………………………………………………………………………………………… 320

6. Assignments……………………………………………………………………………………………………………………… 69
6.1 Continuous assignments………………………………………………………………………………………………. 69
6.2 Procedural assignments……………………………………………………………………………………………….. 73

5. Scheduling semantics…………………………………………………………………………………………………………. 64
5.1 Execution of a model ………………………………………………………………………………………………….. 64
5.2 Event simulation ………………………………………………………………………………………………………… 64
5.3 The stratified event queue……………………………………………………………………………………………. 64
5.4 The Verilog simulation reference model ……………………………………………………………………….. 65
5.5 Race conditions………………………………………………………………………………………………………….. 66
5.6 Scheduling implication of assignments …………………………………………………………………………. 66

Modeling
1.DataFlow modeling
assignments,delays, expressions, operators and operands  (LRM chapter – 4)
2. Behavioral modeling
9. Behavioral modeling………………………………………………………………………………………………………… 118
9.1 Behavioral model overview ……………………………………………………………………………………….. 118
9.2 Procedural assignments……………………………………………………………………………………………… 119
9.3 Procedural continuous assignments …………………………………………………………………………….. 124
9.4 Conditional statement ……………………………………………………………………………………………….. 127
9.5 Case statement …………………………………………………………………………………………………………. 130
9.6 Looping statements …………………………………………………………………………………………………… 134
9.7 Procedural timing controls…………………………………………………………………………………………. 136
9.8 Block statements ………………………………………………………………………………………………………. 145
9.9 Structured procedures ……………………………………………………………………………………………….. 148

3. Gate level modeling
7. Gate and switch level modeling…………………………………………………………………………………………… 75
7.1 Gate and switch declaration syntax……………………………………………………………………………….. 75
7.2 and, nand, nor, or, xor, and xnor gates…………………………………………………………………………… 81
7.3 buf and not gates ………………………………………………………………………………………………………… 82
7.4 bufif1, bufif0, notif1, and notif0 gates…………………………………………………………………………… 83
7.5 MOS switches ……………………………………………………………………………………………………………. 84
7.6 Bidirectional pass switches ………………………………………………………………………………………….. 86
7.7 CMOS switches …………………………………………………………………………………………………………. 86
7.8 pullup and pulldown sources ……………………………………………………………………………………….. 87
7.9 Logic strength modeling ……………………………………………………………………………………………… 88
7.10 Strengths and values of combined signals ……………………………………………………………………… 89
7.11 Strength reduction by nonresistive devices…………………………………………………………………… 102
7.12 Strength reduction by resistive devices………………………………………………………………………… 102
7.13 Strengths of net types………………………………………………………………………………………………… 102
7.14 Gate and net delays …………………………………………………………………………………………………… 103

4. switch level modelling

FSM:

8. User-defined primitives (UDPs) ………………………………………………………………………………………… 107
8.1 UDP definition …………………………………………………………………………………………………………. 107
8.2 Combinational UDPs ………………………………………………………………………………………………… 111
8.3 Level-sensitive sequential UDPs ………………………………………………………………………………… 112
8.4 Edge-sensitive sequential UDPs …………………………………………………………………………………. 112
8.5 Sequential UDP initialization …………………………………………………………………………………….. 113
8.6 UDP instances………………………………………………………………………………………………………….. 115
8.7 Mixing level-sensitive and edge-sensitive descriptions………………………………………………….. 116
8.8 Level-sensitive dominance…………………………………………………………………………………………. 117

18. Value change dump (VCD) files………………………………………………………………………………………… 324
18.1 Creating the four state value change dump file …………………………………………………………….. 324
18.2 Format of the four state VCD file ……………………………………………………………………………….. 329
18.3 Creating the extended value change dump file ……………………………………………………………… 339
18.4 Format of the extended VCD file………………………………………………………………………………… 343
19. Compiler directives………………………………………………………………………………………………………….. 350
19.1 `celldefine and `endcelldefine…………………………………………………………………………………….. 350
19.2 `default_nettype ……………………………………………………………………………………………………….. 350
19.3 `define and `undef …………………………………………………………………………………………………….. 351
19.4 `ifdef, `else, `elsif, `endif, `ifndef ……………………………………………………………………………….. 353
19.5 `include …………………………………………………………………………………………………………………… 357
19.6 `resetall……………………………………………………………………………………………………………………. 357
19.7 `line ………………………………………………………………………………………………………………………… 358
19.8 `timescale ………………………………………………………………………………………………………………… 358
19.9 `unconnected_drive and `nounconnected_drive ……………………………………………………………. 360

Verilog premitives

Verilog premitivesVerilog provides standard premitives, such as and, nand, or, nor, and not.These are known as built in premitives.

Primitives built by designer is referred as user defined premitives. (UDP).

Based on the behaviour , can be devided as two types.
1. Combinational UDP’s
2. Behavioural UDP’s

Verilog DataTypes

Data Types:
Data types is designed to represent the data storage and transmission elements.Value Set.
Verilog supports four values.
Value Condition in Hardware
0 logic Zero, False condition
1 logic One,  True condition
x Unknown logic value
z High impledence/Floating stateThere are two main groups of data types based on way that they are assigned and hold the values, also represent different hardware structures :
1.Net data types.
2.Variable data types

1. Net data Types:
Net is not a keyword, but represents a class of data types such as wire, wand, wor, tri, triand, trior, tri0, tri1 etc.

The net data types shall represent physical connections between structural entities, such as gates.
A net shall not store a value (except for the trireg net).
Value of net is based on drivers, such as a continuous assignment or a gate.
Undriven net shall have a value of high-impedance (z)

wire a;     //wire a
wire a = 0; //Wire a, with initialized to ‘0’

2. Variable data types:
Variable is not a keyword, but represents a class of data types such as integer, real, realtime, reg, time etc.

A variable is an abstraction of a data storage element.
it stores the value until next assignment.
Uninitialized value of variables is Unknown Value (x) except real and realtime (shall be 0.0).

Vectors
Sclar  – One bit width data type
Vector – multiple bit width data type

Data type (Net/variable) can be decalred as vectors.
if bit width is not specified, default is one bit width.

wirea; //Scalar
wire [2:0] b; //wire b, with width three-bit. Vector

rega; //Scalar
reg [2:0] b; //reg b, with width three-bit. Vector

More on Variable Data Types:
regs/registers:
regs are declared by the keyword reg
default value of reg data type is ‘x’
Integers:
integers are declared by the keyword integer
An integer is a general-purpose variable used for manipulating quantities
time:
A time variable is used for storing and manipulating simulation time quantities (Usefull for debugging purposes)
real:

real are declared by the keyword real
Used to to store real value, can be specified in decimal notation (ex. 1.23) or scentific notaion (ex. 2e3 or 2 X 10^3)

Arrays:

An array is a group of elements that can be 1-bit or n-bit wide.
Array can be dclared for both NET and Variable data types.

Array Declaration:
<data_type> <v_width> <v_name> <v_depth>;

reg var_1;        //var with width 1-bit
reg var_2[31:0];  //array of 32 elements with each element width 1-bit
reg var_2[0:31];  //array of 32 elements with each element width 1-bit
reg var_3[32]; //Invalid declaration

reg [1:0] var_4[31:0];  //array of 32 elements with each element width 2-bit
reg [0:1] var_4[31:0];  //array of 32 elements with each element width 2-bit

reg   var_5 [1:0][2:0]; //two dimensional array 2×3 with each element width 1-bit
var_5[0][0]
var_5[0][1]
var_5[0][2]

var_5[1][0]
var_5[2][1]
var_5[3][2]
reg [0:1] var_6 [1:0][2:0]; //two dimensional array 2×3 with each element width 2-bit

Array assignmnet:
var_1 = 0;

var_2    = 0; //Invalid assignment – attempt to assign to complete array
var_2[0] = 0; //Assigning ‘0’ to 0th index of array

var_4[2]  = 2; //Assigning ‘2’ to 3rd index of array

var_5[1][0] = 1; //Assigning ‘1’ to [0]th index of [1] array

Parameters:
Parameters do not belong to either the variable or the net data type group.
Parameters are not variables, they are constants.
Parameters are declared with the keyword parameter.

parameter abc = 6;   //defines abc as constant value 6
parameter def = 6.3; //defines def as real parameter

 

 

 

Verilog Lexical Tokens

A lexical token is a sequence of characters that can be treated as a unit in the grammar of the programming languages.

Example of tokens:

    • Type token
      • id, number, real, . . .
    • Punctuation tokens
      • if, void, return, . . .
    • Alphabetic tokens
      • keywords

Below are the types of lexical tokens in Verilog,

  • Whitespace
  • Comments
  • Operator
  • Number
  • String
  • Identifier
  • Keyword

White Spaces

What is whitespace?

Whitespace is any string of text composed only of spaces, tabs, or line breaks.

The following is a commented Whitespace program, where each Space, Tab, or Linefeed character is preceded by the identifying comment “S”, “T”, or “L”, respectively: 

S S T        S T        S S L
T        L
S S S ST        T        S S T        S T        L
T        L
S S T        T        S T        T        L
T        L

S S L
L

Comments

A comment is a programmer-readable explanation or annotation in the source code. They are added to make the source code easier for humans to understand, and are generally ignored by compilers and interpreters.

Syntax of Verilog comments,

The Verilog HDL has two forms to introduce comments.

  1. A one-line comment shall start with the two characters // and end with a newline
  2. A block comment shall start with /* and end with */
Comments in Verilog

Operators

Operators are symbols that tell the compiler to perform specific mathematical or logical manipulations. Below are the different categories of operators, details of each will be described in later sections.

1. Arithmetic

2. Relational

3. Bitwise

4. Logical

5. Assignment

6. Increment

7. Miscellaneous

Verilog Tutorial Videos

by: EDA Playground

This tutorial covers Verilog design, simulation, waveform viewing and debugging.There are 10 videos explains verilog with example code.This tutorial uses the free web browser based EDA Playground simulator. under the each video you can find link to the complete example code.
You can simulate and view the waveform on clicking complete code.complete code will redirect you to the EDA Playground where the example codes were saved,with this you are not required to type the code again, just you can run the simulation and check the result,view the waveform.

  
Complete Code                                                                      Complete Code

   
Complete Code                                                                      Complete Code

   
Complete Code                                                                      Complete Code

   
Complete Code                                                                  Complete Code

   
Complete Code                                                                      Complete Code