Systemverilog Queue

Queue in SystemVerilog

A queue is a variable-size, ordered collection of homogeneous elements.

  • like a dynamic array, queues can grow and shrink
  • queue supports adding and removing elements anywhere

Queues are declared using the same syntax as unpacked arrays, but specifying $ as the array size. In queue 0 represents the first, and $ representing the last entries.

A queue can be bounded or unbounded.

  • bounded queue – queue with the number of entries limited or queue size specified
  • unbounded queue – queue with unlimited entries or queue size not specified

Queue Declaration

data_type queue_name[$];

where:
data_type     – data type of the queue elements.
queue_name – name of the queue.

Queue Declaration Example

   bit    queue_1[$];     // queue of bits  (unbound queue)
   int    queue_2[$];     // queue of int  
   byte   queue_3[$:255]; // queue of byte (bounded queue with 256 entries)
   string queue_4[$];     // queue of strings

Queue Initialization

   queue_1  = {0,1,2,3};  
   queue_4  = {“Red”,"Blue”,"Green”};

Unbounded Queue

SystemVerilog queue
SystemVerilog queue

Bounded Queue

SystemVerilog Bounded queue
SystemVerilog Bounded queue

Queue Methods

Method Description
size() returns the number of items in the queue
insert() inserts the given item at the specified index position
delete() deletes the item at the specified index position
push_front() inserts the given element at the front of the queue
push_back() inserts the given element at the end of the queue
pop_front() removes and returns the first element of the queue
pop_back() removes and returns the last element of the queue

Queue Methods Example

Unbounded Queue Declaration, Initialization, Size, Insert and Delete Method

This example shows the declaration and usage Queue methods.

module queues_array;
  //declaration
  bit    [31:0] queue_1[$]; //unbounded queue
  string  queue_2[$];  
  
  initial begin
    //Queue Initialization:
    queue_1 = {0,1,2,3};
    queue_2 = {"Red","Blue","Green"};
    
    //Size-Method
    $display("----- Queue_1 size is %0d  -----",queue_1.size());
    foreach(queue_1[i]) $display("\tqueue_1[%0d] = %0d",i,queue_1[i]);    
    $display("----- Queue_2 size is %0d  -----",queue_2.size());
    foreach(queue_2[i]) $display("\tqueue_2[%0d] = %0s",i,queue_2[i]);
    
    //Insert-Method
    queue_2.insert(1,"Orange");
    $display("----- Queue_2 size  after inserting Orange is %0d  -----",queue_2.size());
    foreach(queue_2[i]) $display("\tqueue_2[%0d] = %0s",i,queue_2[i]);
    
    //Delete Method
    queue_2.delete(3);
    $display("----- Queue_2 size after Delete is %0d  -----",queue_2.size());
    foreach(queue_2[i])$display("\tqueue_2[%0d] = %0s",i,queue_2[i]);
  end

endmodule

Simulator Output:

----- Queue_1 size is 4 -----
queue_1[0] = 0
queue_1[1] = 1
queue_1[2] = 2
queue_1[3] = 3
----- Queue_2 size is 3 -----
queue_2[0] = Red
queue_2[1] = Blue
queue_2[2] = Green
----- Queue_2 size after inserting Orange is 4 -----
queue_2[0] = Red
queue_2[1] = Orange
queue_2[2] = Blue
queue_2[3] = Green
----- Queue_2 size after Delete is 3 -----
queue_2[0] = Red
queue_2[1] = Orange
queue_2[2] = Blue

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Queue, push_front(), push_back(), pop_front() and pop_back() Method

SystemVerilog Queue Operations
SystemVerilog Queue Operations
module queues_array;
  //declaration
  bit    [31:0] queue_1[$]; 
  int    lvar;  
  
  initial begin
    //Queue Initialization:
    queue_1 = {0,1,2,3};
    
    //Size-Method
    $display("\tQueue_1 size is %0d",queue_1.size());   
    
    //Push_front Method
    queue_1.push_front(22);
    $display("\tQueue_1 size after push_front is %0d",queue_1.size());
    
    //Push_back  Method
    queue_1.push_back(44);
    $display("\tQueue_1 size after push_back is %0d",queue_1.size());

 //Pop_front Method
 lvar = queue_1.pop_front();
    $display("\tQueue_1 pop_front value is %0d",lvar);

 //Pop_back Method
 lvar = queue_1.pop_back();
    $display("\tQueue_1 pop_back value is %0d",lvar);
  end
endmodule

Simulator Output:

Queue_1 size is 4
Queue_1 size after push_front is 5
Queue_1 size after push_back is 6
Queue_1 pop_front value is 22
Queue_1 pop_back value is 44

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Bounded queue declaration and accessing

The number of entries of the bounded queue is limited, push_back to the bounded queue (after the queue full condition) will not impact any changes to the queue.  push_front to the bounded queue (after the queue full condition) will delete the last entry from queue and stores a new entry in the 0th index of the queue.

SystemVerilog Bounded Queue Operations
SystemVerilog Bounded Queue Operations
module queues_array;
  //declaration
  int    queue[$:2];
  int    index;
  int  temp_var;
   
  initial begin
    //Queue Initialization:
    queue = {7,3,1};
     
    $display("Queue elements are,");
    $display("\tqueue = %p",queue);
    
    queue.push_back(10);
    
    $display("After push_back Queue elements are,");
    $display("\tqueue = %p",queue);
    
    queue.push_front(10);
    
    $display("After push_front Queue elements are,");
    $display("\tqueue = %p",queue);
  end
 
endmodule

Simulator Output:

Queue elements are,
queue = '{7, 3, 1}
After push_back Queue elements are,
queue = '{7, 3, 1}
After push_front Queue elements are,
queue = '{10, 7, 3}

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Accessing random element of queue

In the below example, random queue entry will be accessed by using index. Unlike pop_front/pop_back option queue entry will not get deleted on accessing with an index of the queue.

module queues_array;
  //declaration
  int    queue[$];
  int    index;
  int  temp_var;
   
  initial begin
    //Queue Initialization:
    queue = {7,3,1,0,8};
     
    $display("----- Queue elements with index -----");
    foreach(queue[i]) 
      $display("\tqueue[%0d] = %0d",i,queue[i]);
    $display("-------------------------------------\n");
    
    $display("Before Queue size is %0d",queue.size());
    repeat(2) begin //{
      index    = $urandom_range(0,4); //index of queue is from 0 to 4
      temp_var = queue[index];
      $display("Value of Index %0d in Queue is %0d",index,temp_var);
    end //} 
    $display("After Queue size is %0d",queue.size());
  end
endmodule

Simulator Output:

----- Queue elements with index -----
queue[0] = 7
queue[1] = 3
queue[2] = 1
queue[3] = 0
queue[4] = 8
-------------------------------------
Before Queue size is 5
Value of Index 3 in Queue is 0
Value of Index 0 in Queue is 7
After Queue size is 5

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Deleting random element of queue with index

Calling queue.delete(index) method will delete the entry stored with ‘index’.

module queues;
  //declaration
  int    queue[$];
  int    index;
  int  temp_var;
   
  initial begin
    //Queue Initialization:
    queue = {7,3,1,0,8};
     
    $display("Queue entries are %p",queue);
    $display("Before Queue size is %0d",queue.size());
    index    = $urandom_range(0,4); //index of queue is from 0 to 4
    $display("Index %0d is deleted",index);
    queue.delete(index);
    $display("After Queue size is %0d",queue.size());
    $display("Queue entries are %p",queue);
   
    $display("\nQueue entries are %p",queue);
    $display("Before Queue size is %0d",queue.size());
    index    = $urandom_range(0,3); //index of queue is from 0 to 4
    $display("Index %0d is deleted",index);
    queue.delete(index);
    $display("After Queue size is %0d",queue.size());
    $display("Queue entries are %p",queue);    
  end
endmodule

Simulator Output:

Queue entries are '{7, 3, 1, 0, 8}
Before Queue size is 5
Index 3 is deleted
After Queue size is 4
Queue entries are '{7, 3, 1, 8}

Queue entries are '{7, 3, 1, 8}
Before Queue size is 4
Index 0 is deleted
After Queue size is 3
Queue entries are '{3, 1, 8}

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Deleting complete queue

Calling queue.delete() method will delete the complete queue, which leads to the deletion of all the entries of the queue.

module qu_delete;
  //queue declaration
  int qu[$];  
  
  initial begin

    qu.push_back(2);
    qu.push_back(13);
    qu.push_back(5);
    qu.push_back(65);
    
    $display("[Before-Delete] Queue size is %0d",qu.size());
    qu.delete();
    $display("[After -Delete] Queue size is %0d",qu.size());    
    
  end
endmodule

Simulator Output:

[Before-Delete] Queue size is 4
[After -Delete] Queue size is 0

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Systemverilog Associative Array

Associative array SystemVerilog

  • Associative array Stores entries in a sparse matrix
  • Associative arrays allocate the storage only when it is used, unless like in the dynamic array we need to allocate memory before using it
  • In associative array index expression is not restricted to integral expressions, but can be of any type
  • An associative array implements a lookup table of the elements of its declared type. The data type to be used as an index serves as the lookup key and imposes an ordering

When the size of the collection is unknown or the data space is sparse, an associative array is a better option.

Dynamic arrays are useful for contiguous collections of variables whose number changes dynamically.

Array Declaration

 data_type array_name [ index_type ];

where:
data_type – data type of the array elements.
array_name – name of the associative array.
index_type – data-type to be used as an index, or *.
* indicates the array is indexed by any integral expression of arbitrary size.

Array Example

 int a_array1[*] ;            // associative array of integer (unspecified index)
 bit [31:0] a_array2[string]; // associative array of 32-bit, indexed by string 
 ev_array [myClass];          //associative array of event,indexed by class
SystemVerilog Associative array
SystemVerilog Associative array

Associative Array Methods

Method Description
num() returns the number of entries in the associative array
delete(index) removes the entry at the specified index.exa_array.delete(index)
exists(index) returns 1 if an element exists at the specified index else returns 0
first(var) assigns the value of first index to the variable var
last(var) assigns the value of last index to the variable var
next(var) assigns the value of next index to the variable var
prev(var) assigns the value of previous index to the variable var

Associative Array Examples

num(), first() and last() method’s

Example-1 : Associative Array Declaration, num(), first() and last() method’s.

module associative_array;
  //array declaration
  int a_array[*];  
  int index;
  
  initial begin
    //allocating array and assigning value to it 
    repeat(3) begin
      a_array[index] = index*2;
      index=index+4;
    end

    //num() –Associative array method
    $display("\tNumber of entries in a_array is %0d",a_array.num());
    $display("--- Associative array a_array entries and Values are ---");
    foreach(a_array[i]) $display("\ta_array[%0d] \t = %0d",i,a_array[i]);
    $display("--------------------------------------------------------");
    
    //first()-Associative array method
    a_array.first(index);
    $display("\First entry is \t a_array[%0d] = %0d",index,a_array[index]);

    //last()-Associative array method
    a_array.last(index);
    $display("\Last entry is \t a_array[%0d] = %0d",index,a_array[index]);
  end
endmodule

Simulator Output:

Number of entries in a_array is 3
--- Associative array a_array entries and Values are ---
a_array[0] = 0
a_array[4] = 8
a_array[8] = 16
--------------------------------------------------------
First entry is a_array[0] = 0
Last entry is a_array[8] = 16

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exists(), prev() and last() method’s

Example-2 : Associative Array – exists(), prev() and last() method’s.

module associative_array;
  //array declaration
  int a_array[*];  
  int index;
  
  initial begin
    //allocating array and assigning value to it 
    repeat(3) begin
      a_array[index] = index*2;
      index=index+4;
    end
    
    //exists()-Associative array method
    if(a_array.exists(8))
      $display("Index 8 exists in a_array");
    else 
      $display("Index 8 doesnt exists in a_array");
    
    //last()-Associative array method
    a_array.last(index);
    $display("Last entry is a_array[%0d] = %0d",index,a_array[index]);
    
    //prev()-Associative array method
    a_array.prev(index);
    $display("entry is a_array[%0d] = %0d",index,a_array[index]);
    
    //next()-Associative array method
    a_array.next(index);
    $display("entry is a_array[%0d] = %0d",index,a_array[index]);
  end
endmodule

Simulator Output:

Index 8 exists in a_array
Last entry is a_array[8] = 16
entry is a_array[4] = 8
entry is a_array[8] = 16

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bit and string index type

Example-3: Associative Array – bit and string index type.

module associative_array;
  //array declaration
  int a_array1[bit [7:0]]; //index type is bit [7:0] and entry type is int
  bit a_array2[string]   ; //index type is string and entry type is bit
  
  initial begin
    //allocating array and assigning value to it 
    a_array1[5] = 10;
    a_array1[8] = 20;
        
    a_array2["GOOD_PKT"] = 1;
    a_array2["BAD_PKT"]  = 0;
       
    foreach(a_array1[index]) 
      $display("a_array1[%0d] = %0d",index,a_array1[index]);
    foreach(a_array2[index]) 
      $display("a_array2[%0s] = %0d",index,a_array2[index]);
  end
endmodule

Simulator Output:

a_array1[5] = 10
a_array1[8] = 20
a_array2[BAD_PKT] = 0
a_array2[GOOD_PKT] = 1

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Deleting complete Assoc Array

Example-4: Deleting complete Associative Array

Calling array.delete() method will delete the complete array, which leads to the deletion of all the entries of an array.

module associative_array;
  //array declaration
  int a_array[*];  
  int index;
  
  initial begin
    //allocating array and assigning value to it 
    repeat(3) begin
      a_array[index] = index*2;
      index=index+4;
    end
    
    $display("[Before-Delete] Associative array size is %0d",a_array.size());
    a_array.delete();
    $display("[After -Delete] Associative array size is %0d",a_array.size());    
    
  end
endmodule

Simulator Output:

[Before-Delete] Associative array size is 3
[After -Delete] Associative array size is 0

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SystemVerilog Enumerations

SystemVerilog enum data type

An enumerated type defines a set of named values. The simplest enumerated type declaration contains a list of constant names and one or more variables.

In the following example, colors are defined to be variable of the unnamed enumerated int type that includes the members red, green, blue, yellow, white, black.

enum { red, green, blue, yellow, white, black } Colors;

The actual values are defaulted to integers starting at 0 and then increase. in the above example by default variable will get the default value of 0,1,2,3,4,5 respectively from red. The values can be set for the names and also values can be set for some of the names and not set for other names. A name without a value is automatically assigned an increment of the value of the previous name.

In the following example value is set for red = 0, blue = 4, white = 10.

enum { red=0, green, blue=4, yellow, white=10, black } Colors;

green, yellow, black automatically assigned to the increment-value of 1,5,11 respectively.

If an automatically incremented value is assigned elsewhere in the same enumeration, this shall be a syntax error.

In the below example yellow will get the increment-value of 5, the value of white is set with 5. this will cause the syntax error.

enum { red=0, green=0, blue=4, yellow, white=5, black=6 } Colors

Defining new data types as enumerated types

A type name can be given so that the same type can be used in many places.

typedef enum {GOOD, BAD} pkt_type; 

pkt_type pkt_a; // named type

enum methods

Method Description
first() returns the value of the first member of the enumeration
last() returns the value of the last member of the enumeration
next() returns the value of next member of the enumeration
next(N) returns the value of next Nth member of the enumeration
prev() returns the value of previous member of the enumeration
prev(N) returns the value of previous Nth member of the enumeration
num() returns the number of elements in the given enumeration
name() returns the string representation of the given enumeration value

enum examples

Example-1 : Enumeration Type [DataTypes] This example shows how to declare enum.

module enum_datatype;
  //declaration
  enum { red, green, blue, yellow, white, black } Colors;
 
  //display members of Colors
  initial begin
    Colors = Colors.first;  
   
    for(int i=0;i<6;i++) begin
       $display("Colors :: Value of  %0s \t is = %0d",Colors.name,Colors);
       Colors = Colors.next;      
    end
  end
endmodule

Simulator Output

Colors :: Value of red is = 0
Colors :: Value of green is = 1
Colors :: Value of blue is = 2
Colors :: Value of yellow is = 3
Colors :: Value of white is = 4
Colors :: Value of black is = 5

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Example-2 : Enumeration Type [DataTypes]

This example shows how to set other than default values to an enum.

module enum_datatype; 
  //declaration 
  enum { red=0, green, blue=4, yellow, white=10, black } Colors;
 
  //display members of Colors
  initial begin
    Colors = Colors.first;
 
    for(int i=0;i<6;i++) begin  
     $display("Colors :: Value of  %0s \t is = %0d",Colors.name,Colors);
     Colors = Colors.next;      
    end
  end
endmodule

Simulator Output

Colors :: Value of red is = 0
Colors :: Value of green is = 1
Colors :: Value of blue is = 4
Colors :: Value of yellow is = 5
Colors :: Value of white is = 10
Colors :: Value of black is = 11

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SystemVerilog typedef class

typedef class

A typedefis used to provide a forward declaration of the class.
In some cases, the class needs to be instantiated before the class declaration. In these kinds of situations, the typedef is used to provide a forward declaration of the class.

typedef syntax

typedef class class_name;

typedef examples

Without typedef

In the below example,
There are two classes c1 and c2.
c2 is instantiated inside c1 and c1 inside c2. Both classes need the handle of each other. As execution will happen in sequential order.
Dependency between both the classes leads to a compilation error.

//class-1
class c1;
  c2 c;    //using class c2 handle before declaring it.
endclass

//class-2
class c2;
  c1 c;
endclass
 
module typedef_class;
  initial begin
    c1 class1;
    c2 class2;
    $display("Inside typedef_class");
  end
endmodule

Simulator Output

Error-[SE] Syntax error
Following verilog source has syntax error :
token 'c2' should be a valid type. Please declare it virtual if it
is an Interface.
"testbench.sv", 6: token is ';'
c2 c;

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With typedef

The compilation error of the above example can be avoided by using a typedef.

typedef class c2;
//class-1
class c1;
  c2 c;    //using class c2 handle before declaring it.
endclass

//class-2
class c2;
  c1 c;
endclass
 
module typedef_class;
  initial begin
    c1 class1;
    c2 class2;
    $display("Inside typedef_class");
  end
endmodule

Simulator Output

Inside typedef_class

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SystemVerilog Functions in Constraints

Functions in Constraints

In some cases constraint can’t be expressed in a single line, in such cases function call can be used to constrain a random variable. calling the function inside the constraint is referred to as function in constraints.

  • The function will be written outside the constraint block
  • Constraint logic shall be written inside the function as function definition and function call shall be placed inside the constraint block
  • Functions shall be called before constraints are solved, and their return values shall be treated as state variables.
constraint constraint_name { var = function_call(); };

Functions in constraints example

In the below example,
The function is called inside the constraint.

class packet;
  rand bit [3:0] start_addr;
  rand bit [3:0] end_addr;
  
  constraint start_addr_c { start_addr == s_addr(end_addr); }
  
  function bit [3:0] s_addr(bit [3:0] e_addr);
    if(e_addr < 4) 
      s_addr = 0;
    else 
      s_addr = e_addr - 4;
  endfunction
  
endclass

module func_constr;
  initial begin
    packet pkt;
    pkt = new();
    repeat(3) begin
      pkt.randomize();
      $display("\tstart_addr = %0d end_addr =",pkt.start_addr,pkt.end_addr);
    end
  end
endmodule

Simulator Output

start_addr = 9 end_addr =13
start_addr = 2 end_addr = 6
start_addr = 0 end_addr = 1

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SystemVerilog Functions

functions

A Function can contain declarations of range, returned type, parameters, input arguments, registers, and events.

  • A function without a range or return type declaration returns a one-bit value
  • Any expression can be used as a function call argument
  • Functions cannot contain any time-controlled statements, and they cannot enable tasks
  • Functions can return only one value

SystemVerilog function can be,

  • static
  • automatic

Static Function

Static functions share the same storage space for all function calls.

Automatic Function

Automatic functions allocate unique, stacked storage for each function call.

SystemVerilog allows,

  • to declare an automatic variable in static functions
  • to declare the static variable in automatic functions
  • more capabilities for declaring function ports
  • multiple statements within a function without requiring a begin…end or fork…join block
  • returning from the function before reaching the end of the function
  • Passing values by reference, value, names, and position
  • default argument values
  • function output and inout ports
  • the default direction of argument is input if no direction has been specified.
  • default arguments type is logic if no type has been specified.

function examples

function arguments in parentheses

module sv_function;
  int x;
  //function to add two integer numbers.
  function int sum(input int a,b);
    sum = a+b;   
  endfunction

  initial begin
    x=sum(10,5);
    $display("\tValue of x = %0d",x);
  end
endmodule

Simulator Output

Value of x=15

Click to execute on

function arguments in declarations and mentioning directions

module sv_function;
  int x;

  //function to add two integer numbers.
  function int sum;
    input int a,b;
    sum = a+b;   
  endfunction
  initial begin
    x=sum(10,5);
    $display("\tValue of x = %0d",x);
  end
endmodule

Simulator Output

Value of x = 15

Click to execute on

function with return value with the return keyword

In the below example,
arguments in declarations and directions, return value is specified using the return statement.

module sv_function;
  int x;

  //function to add two integer numbers.
  function int sum;
    input int a,b;
    return a+b;   
  endfunction

  initial begin
    x=sum(10,5);
    $display("\tValue of x = %0d",x);
  end
endmodule

Simulator Output

Value of x = 15

Click to execute on

Void function

The example below shows usage of void function, void function,(function with no return value)

module sv_function;
  int x;
  //void function to display current simulation time 
  function void current_time;
    $display("\tCurrent simulation time is %0d",$time);    
  endfunction
 
  initial begin
    #10;
    current_time();
    #20;
    current_time();
  end
endmodule

Simulator Output

Current simulation time is 10
Current simulation time is 30

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discarding function return value

The function return value must be assigned to a variable or used in an expression.

Calling a function without return value assigned to a variable can result in a warning message. SystemVerilog void data type is used to discard a function’s return value without any warning message.

module sv_function;
  int x;
   //function to add two integer numbers. 
  function int sum;
    input int a,b;
    return a+b;    
  endfunction
 
  initial begin
    $display("Calling function with void");
    void'(sum(10,5));
  end
 endmodule

Simulator Output

Calling function with void

Click to execute on

function call as an expression

module sv_function;
  int x;
  //function to add two integer numbers. 
  function int sum;
    input int a,b;
  return a+b;    
  endfunction
  initial begin
    x = 10 + sum(10,5);
    $display("\tValue of x = %0d",x);
  end
endmodule

Simulator Output

Value of x = 25

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SystemVerilog Tutorial

SystemVerilog tutorial for beginners

Introduction Introduction About SystemVerilog Introduction to Verification and SystemVerilog
Data Types Index Integer, Void String, Event User-defined
Enumerations Enum examples, Class
Arrays Index Fixed Size
Arrays
Packed and
Un-Packed
Dynamic
Array
Associative
Array
Queues
Procedural Statements and Flow Control Index Blocking
Non-Blocking assignments
Unique-If
Priority-If
while, do-while
foreach
enhanced for loop
repeat, forever break and continue
Named Blocks, Statement Labels disable block and disable statements Event Control
Processes Index fork-join fork-join_any fork-join_none
wait-fork disable-fork
Tasks and Functions Index Tasks Functions Argument passing
Import & Export Functions
Classes Index Classes This Keyword Constructors
Static Class Properties & Methods Class Assignment Shallow Copy
Deep Copy Parameterized Classes Inheritance
Overriding Class Members Super Keyword Casting
Data Hiding and Encapsulation Abstract Classes
Virtual Methods
Class Scope Resolution Operator ::
Extern methods typedef Classes
Randomization & Constraints Index Randomization
Disable randomization
Randomization methods Constraint Block
Inside Operator Weighted distribution Implication and if-else
Iterative in constraint block Constraint mode disable
Static constraints
In line constraints
Function in constraints
Soft constraints Unique constraints Bidirectional constraints
Solve Before Random System Methods
IPC Semaphore
Semaphore examples
Mailbox Event
Event examples
Scheduling Semantics Program Block Interface
Virtual Interface Modport Clocking Blocks
Assertions Index Assertions SVA Building Blocks SVA Sequence
Implication Operator Repetition Operator SVA Built In Methods
Ended and Disable iff Variable Delay in SVA
Coverage Index Coverage Functional Coverage Cross Coverage
Coverage Options Parameters and `define

Array Manipulation Methods Index Array ordering methods Array reduction methods
Examples
Array locator methods
Array iterator index querying Array Slice Randomize Variable
Array randomization Dynamic array reduction Associative array reduction
Queue Randomization Callback Callback example
Multi dimensional dynamic array 2d array Array methods Assoc array find index
SystemVerilog DPI SystemVerilog Struct Diff between struct and array Int vs Integer
Enum Cast Enum of logic bit int Print enum as string Logic vs Wire
Code library Quiz Queue randomization Interview questions

 

SystemVerilog TestBench
SystemVerilog TestBench and Its components
Adder – TestBench Example
Memory Model – TestBench Example